1. Field
Example embodiments relate to an on-die termination (ODT) circuit of a semiconductor memory device and/or a method of controlling the same, and for example, to an ODT synchronous buffer of an ODT circuit and/or a method of controlling the same.
2. Description of Related Art
A frequency of a signal bus of a system employing a dynamic random access memory (DRAM) rapidly increases in order to achieve a higher-speed operation. Accordingly, various studies on a bus termination technique for solving an impedance mismatching problem to minimize signal integrity distortion have been carried out. These studies show that a method using on-die termination (ODT) may be more advantageous than a method using mother board termination (MBT) in systems having a stub bus structure.
ODT may include a termination structure in which bus termination is performed at input/output ports of a memory set in a memory module. An ODT circuit is an impedance matching circuit, which is also referred to as an on-chip termination circuit, and is located near a pad in an integrated circuit chip.
A period of time from if an external ODT command is applied to the ODT circuit to when ODT is carried out is defined as a clock latency.